Guide on Crafting Broadband Loop Phase-Locked Phase Frequency Synthesizers for Top-tier Performance (Installment 1)
In a recent development, a team of top technical professionals in frequency synthesizers, radio/radar, and communications systems has produced a high-performance PLL frequency synthesizer with a wide loop bandwidth and low phase noise comparable to direct synthesizers.
The synthesizer project, spearheaded by a particular staff scientist and subject-matter expert, is a testament to the team's expertise in the field. The author of the paper, who worked closely with this team, further solidified and expanded his knowledge of PLLs and indirect (PLL) synthesizers through his involvement in the project.
The synthesizer is a single-loop, Type 2 - 2 Order system with a 1 Order active PI loop filter, used as a local oscillator in an actual working and fielded high-performance receiver. Its specifications include an operating band of 22.5 - 39.9 GHz, channel spacing of 200 MHz, reference frequency of 400 MHz, phase continuity, stability, SSB phase noise, spurious, switching time, output power and flatness, DC operating power, and operating temperature range.
The special technique discussed in the paper is for producing very wide loop bandwidths in high-frequency PLLs, achieving low phase noise rivaling that of direct synthesizers. This is achieved by taking the loop filter and splitting the proportional and integral functions into two separate parallel paths, each with its own active devices, and recombining or summing the outputs to provide a common VCO control signal.
For those interested in designing such PLL frequency synthesizers, a recommended starting point is a detailed three-part series published in 2025 titled "How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers." This series explains techniques to achieve very wide loop bandwidths in high-frequency PLLs, delivering very low phase noise, rivaling direct synthesizers, while maintaining advantages such as lower size, weight, power (SWaP), cost, and complexity typical of PLLs.
Further insights can be gained by studying phase noise optimization techniques in PLL components such as phase-frequency detectors (PFD) and charge pumps (CP). For instance, an 8-channel phased-array CMOS transmitter design discussed in a recent 2025 paper demonstrates careful noise current degeneration and simulation to achieve phase noise floors better than −144 dBc/Hz, indicating design strategies for low PN at close offsets.
Examining wideband RF front-end solutions incorporating synthesizer technologies can provide a system-level perspective on integrating wide-loop BW PLLs to support frequencies up to 55GHz and beyond while minimizing phase noise and complexity.
Understanding the differences and trade-offs with direct synthesizers like Direct Digital Synthesizer (DDS) is also crucial to appreciate what PLL designs must match or exceed in phase noise. DDS can offer extremely fine frequency resolution and low phase noise but have trade-offs in complexity and spectral purity depending on DAC resolution and phase-to-amplitude conversion methods.
By following these recommended steps, one can gain a comprehensive understanding of techniques to design PLL frequency synthesizers with wide loop bandwidth and low phase noise performance similar to direct synthesizers. The synthesizer project serves as a significant step forward in the field of frequency synthesizers, radio/radar, and communications systems, with potential applications in 5G, 6G, satellite communications, and tactical radios.
[1] "How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers," Electronic Design, 2025. [2] "8-channel phased-array CMOS transmitter design with low phase noise," IEEE Transactions on Microwave Theory and Techniques, 2025. [3] "Wideband RF front-end synthesizer designs and integration challenges," IEEE Journal of Solid-State Circuits, 2025. [4] "Direct Digital Synthesizer (DDS) principles," IEEE Transactions on Communications, 2025.
Technology advancements in PLL frequency synthesizers are evident through the production of high-performance devices, as demonstrated by the single-loop, Type 2 - 2 Order system with a wide loop bandwidth and low phase noise comparable to direct synthesizers. By studying papers such as the three-part series "How to Design Very Wide Loop BW High-Performance PLL Frequency Synthesizers," one can learn techniques to design PLL synthesizers with technology that matches or exceeds the low phase noise performance of direct synthesizers.
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