Exploring Borders: Pushing Ahead in the Realm of 3D NAND Memory Technology
In the ever-evolving world of technology, the semiconductor industry is continually pushing the boundaries of innovation to meet the growing demands for data storage. One such area of focus is 3D NAND flash memory, a technology that has played a significant role in the AI boom and is integral to a wide range of electronics, from smartphones to data centers.
Z-Pitch Scaling and its Challenges
To accommodate the increasing need for higher storage density, the industry is pursuing vertical or "z-pitch" scaling, which involves shrinking the space between memory layers. However, this approach can negatively impact the electrical performance of memory cells, leading to reduced threshold voltage, enhanced sub-threshold swing, and decreased retention.
Several enabling technologies are being developed to overcome these challenges. For instance, advancements in nanoimprint lithography (NIL) provide high-throughput, deep-nanoscale 3D patterning capabilities relevant to vertically scaling 3D NAND structures. NIL has become an important alternative to extreme ultraviolet (EUV) lithography in enabling fine vertical pitch control at scale, facilitating continued stacking density improvements.
Another crucial technology is fine-pitch 3D interconnect technologies, such as direct bonding interconnects (DBI), which allow scaling of 3D interconnect pitch from below 10 µm down to 1 µm or less. This fine-pitch 3D interconnect capability is essential to maintain electrical connectivity and performance as z-pitch shrinks.
However, maintaining pattern fidelity and overlay accuracy in extreme nanoscale 3D patterning is difficult with conventional lithography. Computational lithography methods like inverse lithography technology (ILT) are being explored to overcome these limitations due to shrinking feature sizes in the vertical dimension.
Mechanical and thermal stress management in densely stacked layers is another challenge that needs to be addressed to prevent degradation and ensure reliable operation as layers get thinner and closer.
Innovations in 3D NAND
Companies are contemplating various methods for tier stacking, including bonding several memory arrays on a single CMOS wafer. In the 3D NAND structure, the memory cells are stacked to form a vertical string and are addressed by horizontal word-lines.
The manufacturing process for the GAA channel in 3D NAND involves stacking alternating layers of conductor and insulator, forming cylindrical holes, and depositing alternating layers of silicon oxide and SiN on the sidewalls of the hole.
The shift from the floating-gate transistor to the charge trap cell is a significant development in 3D NAND. The charge trap cells store charges in insulators, reducing electrostatic coupling between memory cells and improving read and write performance. The charge trap cell acts as the storage device in 3D NAND and resembles a MOSFET with a thin sheet of silicon nitride (SiN) embedded inside the transistor's gate oxide.
Imec is working on new techniques that enable charge trap layer separation (or charge trap cut) in 3D NAND flash, which can increase the memory window of the cell and prevent lateral charge migration. This innovation allows for the airgap to be integrated without slicing the SiN out of the memory cell, achieved by recessing the inter-gate silicon oxide before depositing the ONO stack.
Future of 3D NAND
The memory industry is pushing the GAA-based 3D NAND flash roadmap to its ultimate limits, with companies rolling out 3D NAND flash chips with over 300 oxide/word-line layers stacked on top of each other, and 1,000 layers projected by 2030. To increase the storage density of 3D NAND, companies are investing in several complementary tools, including increasing the number of bits per cell, reducing the x-y pitch of the GAA cell (lateral scaling), and tier stacking.
Imec intends to combine airgap integration and charge trap cut to deliver a complete and scalable solution for the z-pitch scaling challenges in 3D NAND flash. Researchers at imec presented a unique integration scheme for airgaps between adjacent word-lines in 3D NAND, aiming to reduce electrostatic coupling between memory cells.
These developments may allow the memory industry to gradually move towards 100 Gb/mm of data storage, driven primarily by cloud computing and AI applications. The semiconductor industry is turning to several new technologies to cram memory cells more tightly together, including airgap integration and charge trap layer separation. These innovations will be key in carrying the memory roadmap beyond 2030, as the industry reimagines the layout of memory cells with horizontally arranged conduction channels and trench-based architectures.
- Technological advancements in 3D NAND flash memory, such as charge trap cell usage, are integral to the AI boom and various electronics, demonstrating the crucial intersection of science and technology in modern innovation.
- To sustain the electrical connectivity and performance as z-pitch scales down in 3D NAND, fine-pitch 3D interconnect technologies like direct bonding interconnects (DBI) are essential, highlighting the ongoing collaboration between science and technology in the semiconductor industry.
